PCB Capabilities
PCB manufacturing capabilities
Use this page to confirm whether your stack-up, geometry, and finishes fit our standard process window before you open the quote tool. Specs below reflect common production lanes; exotic builds can be reviewed via RFQ.
Board basics
| Parameter | Capability |
|---|---|
| Layer count | 1–20 layers |
| Material | FR-4 (Tg130/150/170), High-Tg, Halogen-free, Aluminum, Rogers / hybrid (on review) |
| Board thickness | 0.4–3.2 mm (standard); up to 4.0 mm on review |
| Board size | 10 × 10 mm – 600 × 500 mm |
| Tg | Tg130 / Tg150 / Tg170 (material dependent) |
Trace & drilling
| Parameter | Capability |
|---|---|
| Outer copper | 0.5–3 oz (up to 6 oz on review) |
| Inner copper | 0.5–2 oz (up to 3 oz on review) |
| Min trace / space | 3 / 3 mil (0.075 / 0.075 mm) |
| Min finished hole | 0.15 mm |
| Hole size tolerance | ±0.05 mm (PTH); ±0.025 mm (NPTH typical) |
| Annular ring | ≥ 0.1 mm (4 mil) recommended |
Solder mask & silkscreen
| Parameter | Capability |
|---|---|
| Solder mask colors | Green, Matte Green, Blue, Red, Yellow, Black, Matte Black, White, Purple |
| Silkscreen colors | White, Black, None |
| Min solder mask dam | 0.1 mm (4 mil) |
Surface finishes
| Parameter | Capability |
|---|---|
| Available finishes | HASL, Lead-free HASL, ENIG, OSP, Immersion Silver, Immersion Tin, Hard Gold |
| ENIG thickness | Au 1–3 µin over Ni 120–200 µin (typical) |
| Hard gold (fingers) | Available with bevel option |
Special processes
| Parameter | Capability |
|---|---|
| Impedance control | Single-ended / differential; ±10% typical |
| Gold fingers | Yes, with optional chamfer |
| Via fill | Resin plug / via in pad (on review) |
| Blind / buried vias | HDI 1–3 step (on review) |
| Castellated holes | Supported |
| V-CUT / scoring | Supported |
| Mouse bites / stamp holes | Supported |
Electrical test
| Parameter | Capability |
|---|---|
| Flying probe | Standard for prototypes / small volume |
| Fixture (bed-of-nails) | Available for volume; NRE may apply |
| AOI | Standard process control |
Extra charges (indicative)
| Parameter | Capability |
|---|---|
| Impedance control | Per stack-up / coupon set |
| Gold fingers + bevel | Per edge / gold area |
| Via in pad / resin plug | Per panel complexity |
| HDI blind/buried | Per step & layer pair |
| Electrical test fixture | One-time NRE |
| Expedite fee | Per lead-time tier (see matrix) |
Final extras appear in the quote breakdown. Values below are typical adders for planning, not a binding price list.
Lead time matrix (working days, fab only)
| Layers | Qty ≤ 20 (Std) | Qty ≤ 20 (Expedite) | Qty 100+ (Std) | Qty 100+ (Expedite) |
|---|---|---|---|---|
| 1–2 L | 3–5 | 24–48 h | 5–7 | 3–4 |
| 4 L | 5–7 | 2–3 | 7–9 | 4–5 |
| 6–8 L | 7–10 | 3–5 | 9–12 | 5–7 |
| 10–12 L | 10–14 | 6–8 | 12–16 | 8–10 |
| 14–20 L | On review | On review | On review | On review |
Calendar days exclude Chinese public holidays. Shipping adds transit time. Exact dates shown at checkout.
File requirements
Submit Gerber (RS-274X), ODB++, or IPC-2581. Clear layer naming speeds DFM and reduces clarification loops.
- Copper: .GTL / .GBL / inner .G1 .G2… (or equivalent ODB++)
- Solder mask: .GTS / .GBS
- Silkscreen: .GTO / .GBO
- Paste (if SMT): .GTP / .GBP
- Drill: Excellon .TXT / .DRL with plated vs non-plated notes
- Board outline: .GKO / .GM1 and units clearly stated (mm preferred)
- Stack-up & impedance notes for controlled-impedance builds
- ZIP one project folder; avoid mixed revisions in the same archive
Ready to price this stack-up?
Jump into the instant PCB quote with your layers, size, and quantity.